關注微信 意見反饋

掃描關注摩爾人半導體招聘

摩爾人招聘
對職位有興趣?上傳您的簡歷無需注冊,即可直接投遞您心儀的職位
Cadence

Principal Design Engineer - FPGA

收藏職位
  • 我要分享
  • 40萬-60萬/年
  • 上海
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全職

職位誘惑: 年終獎金,福利好,老板nice,年底雙薪,股票期權,技術領先

五子棋游戏程序代码 www.jqrog.icu 發布時間: 2019-07-19發布

職位描述

Title: Principal Design Engineer

Job Description
Responsible for designing and developing sub-systems and modules or components of hardware based verification products. In addition modifying, updating and productizing existing hardware based verification products. Perform as individual contributor on FPGA based design projects involving board design, RTL design, verification, productizing and documentation. Work on diverse problems related to FPGA design, simulation or verification issues.
 
Position Requirements:
The position requires BSEE, or equivalent, with a minimum of 5 yrs of industry experience in designing hardware systems.
Must have excellent communication skills, both written and verbal.
Technical expertise in FPGA design for either Altera or Xilinx products is required.
Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired.
RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows.
Verification using with Cadence simulation products is desired.
Experience with scripting languages like Perl, TCL C-shell is strongly recommended.
Experience with PCB tools is also desired.

職位發布者

cadence hr

Sr.Manager&BP

7天

簡歷處理用時

90%

簡歷及時處理率

您還未登錄。已有賬號, 點此登錄,直接投遞

推薦朋友

一鍵投遞
包六肖什么意思 北京pk全能计划软件 850通比牛牛如何稳赢 850通比牛牛怎么赢 北京pk拾赛车高手论坛 广东时时11玩法介绍 如何玩pc稳赚不赔 河内时时彩人工计划软件 彩世界安全下载 时时彩开奖结果 快乐时时计划软件 pk10最牛稳赚单双 重庆时时彩如何看龙虎 mg游戏网页游戏修改器 时时彩包赢公式0369 pk10智能计划苹果版